June 6, 2011 -- Oasys Design Systems has announced that its Chip Synthesis platform, in use in production environments, now includes design-for-test (DFT) capabilities, further extending the speed and capacity of Oasys' RealTime Designer software.
This follows an earlier announcement that the Chip Synthesis platform supports chip-level power analysis and optimization, and has the ability to synthesize a design from the register transfer level (RTL) with UPF or CPF power constraints. These additional features complete the fully integrated Chip Synthesis front-to-back design flow.
The combination of full-chip synthesis and RealTime Designer's DFT capabilities help designers create a better DFT architecture and chip partitioning for DFT. With RealTime Designer, full-chip DFT synthesis can be performed in a single pass with fast turnaround and without the need for complex DFT abstraction and bottom-up flows.
Features include design checking and debugging for various DFT rule violations, test clock analysis, power-domains-aware physical scan chain ordering and lockup-latch insertion. It integrates third-party DFT-compression. Information on pre-inserted DFT logic can be imported in the industry-standard IEEE 1450.6 (CTL) format.
According to Oasys, traditional block-level synthesis tools do a poor job of handling chip-level issues and is the first design tool for physical RTL synthesis of 100-million gate designs. It features a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout.
RealTime Designer follows a "Place First" methodology that takes RTL code, partitions it into blocks, places it in the context of a floorplan and implements each block through to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at RTL and re-implement it until chip-level constraints are met.
Availability and Pricing
The latest version RealTime Designer, with DFT and chip-level power analysis capabilities, is shipping now and is priced from $395,000 for a one-year, time-based license.
Oasys will offer informative and continuous demonstrations of RealTime Designer in Booth #2031 at the 48th Design Automation Conference (DAC) June 6-8 at the San Diego Convention Center in San Diego, Calif.
Go to the Oasys Design Systems website to find additional information.