Page loading . . .

 You are at: The item(s) you requested.Tuesday, October 25, 2016
Vitesse Gigabit Ethernet IP Cores Enable Proliferation of Ethernet Applications  
 Printer friendly
 E-Mail Item URL

June 6, 2011 -- Vitesse Semiconductor Corp. today introduced a portfolio of Gigabit Ethernet intellectual property (IP) cores for simple and efficient integration of 10/ 100/ 1000BASE-T functionality into Ethernet IC solutions for consumer electronics, broadband access, network security, printer, smart grid, storage, and other applications.

With energy efficiency mandates such as Energy Star's upcoming Small Network Equipment specification and IEEE 802.3az 2010 Energy Efficient Ethernet (EEE), low power is critical for new Ethernet products. Vitesse's Gigabit Ethernet IP cores deliver industry-leading power dissipation below 390mW per port and feature Vitesse's EcoEthernet 2.0 power-saving technology. EcoEthernet includes fully compliant IEEE 802.3az EEE that can reduce power by 60% in idle mode. In addition, an ActiPHY-enabled mode reduces power by over 75% for ports with no link.

"Design constraints we faced mandated that we use a highly characterized Gigabit Ethernet PHY technology, and one with extremely low power dissipation," said Cheng-Te Chuang, Corporate Vice President of MediaTek, a vendor already in production with multiple ports of Vitesse's Gigabit Ethernet IP core. "Vitesse's solution embedded all of the necessary transceiver features for our applications to efficiently reach the market with integrated Ethernet connectivity."

Vitesse's Gigabit Ethernet IP core portfolio offers hard and soft macros for maximum flexibility, specifically including:
  • Single port 10/100/1000BASE-T hard macro for TSMC 40LP (VSC9905-01).
  • Four port 10/100/1000BASE-T hard macro for TSMC 65GP (VSC9903-01).
  • Single port 10/100/1000BASE-T hard macro for TSMC 65GP (VSC9902-01).
  • Soft IP package (VSC9901-01) for porting the module-oriented PHY design to other fabrication processes or enabling the technology in ASIC design flows.

The cores are based on a power-efficient voltage-mode architecture with integrated line side resistors and low-EMI line drivers that provide extra margin for meeting residential emission standards. Their cable impairment active correction technology and robust DSP capabilities filter out cable noise and support remote cable diagnostics functionality. Carrier Ethernet (CE) versions of each core are also available. The CE versions offer multiple recovered clock outputs and fast link failover support ideal for use in G.8261 Synchronous Ethernet applications.

The hard macros, each fully routed designs that can improve time-to-market and reduce project risk, are provided with encrypted Verilog models; LVS netlist, GDS-II, and frame view LEF files; timing models; test benches for functional verification and production test-vector generation; Application Programming Interface source code; and documentation. The soft IP package (VSC9901-01) deliverables also include analog schematics, I/O cell netlists, RTL, and Verilog synthesis scripts.


The VSC9901-01, VSC9902-01 and VSC9903-01 are available immediately.

Go to the Vitesse Semiconductor Corp. website to find additional information.

E-mail Vitesse Semiconductor Corp. for more information.

Read more about
Vitesse Semiconductor Corp.

Keywords: ASICs, ASIC design, IP, intellectual property, cores, Gigabit Ethernet, Vitesse Semiconductor,
600/34055 6/7/2011 1105 149
Designer's Mall

Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  1.203125