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Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SOC  
Publication: Design & Reuse
Contributor: Arteris SA
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June 20, 2011 -- This article presents an overview of the design process of an interconnection network, using the technology proposed by Arteris. Section 2 summarizes the various features a NoC is required to implement to be integrated in modern SOCs. Section 3 describes the proposed top-down approach, based on the progressive refinement of the NoC description, from its functional specification (Sect. 4) to its verification (Sect. 8).

The approach is illustrated by a typical use-case of a NoC embedded in a hand-held gaming device. The methodology relies on the definition of the performance behavior and expectation (Sect. 5), which can be early and efficiently simulated against various NoC architectures. The system architect is then able to identify bottle-necks and converge towards the NoC implementation fulfilling the requirements of the target application (Sect. 6).

By Jean-Jacques Lecler and Gilles Baillieu. (Lecler and Baillieu are both with Arteris.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

Read more about
Arteris SA
on SOCcentral.com

Keywords: ASICs, ASIC design, IP, intellectual property, cores, network-on-chip, NoC, on-chip interconnect, Design & Reuse, Arteris, Jean-Jacques Lecler, Gilles Baillieu,
599/34113 6/20/2011 1906 160


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