Page loading . . .

  
 You are at: The item(s) you requested.Thursday, June 20, 2013
Aldec Adds UVM Transaction-Level Visual Debugging  
 Printer friendly
 E-Mail Item URL

July 11, 2011 -- Aldec, Inc. today announced expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization let engineers utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling.

"Our UVM 1.0 implementation combines the proven debugging capabilities of Riviera-PRO with an industry-standard approach to building reusable and expandable verification environments, providing a more natural way for engineers to comprehend and debug sophisticated verification environments," said Dave Rinehart, Vice President, Aldec, Inc.

Riviera-PRO allows analyzing transaction data using the existing Waveform Viewer tool together with the new Transaction Data Viewer that represents transactions as a spreadsheet that offers rich navigation and filtering capabilities. All the debugging tools are well integrated with each other and allow for efficient analysis of transaction-level information, including the cross-probing and viewing of transaction attributes, relations and linked signals. Based on such a broad range of information about the interactions between testbench and design under test, Riviera-PRO users have extensive visibility into their verification environments. About Riviera-PRO Riviera-PRO is a complete verification platform that supports the latest versions of industry standard verification libraries such as SystemVerilog UVM 1.0, OVM 2.1.2 and VMM 1.1.1a. In combination with advanced debugging tools, it makes Riviera-PRO an ideal platform for building up layered, coverage driven, constrained-random environments for functional verification of sophisticated ASIC and FPGA designs.

Availability

The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of 2011.06 at no cost to users with a valid maintenance contract and SystemVerilog verification support.

Go to the Aldec, Inc. website to find additional information.

E-mail Aldec, Inc. for more information.

Read more about
Aldec, Inc.
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, transaction level modeling, transaction-level modeling, TLM, SystemVerilog, Universal Verification Methodology, UVM, Aldec, Riviera-PRO
600/34230 7/11/2011 682 114
Designer's Mall
4th Of July countdown banner
0.5166016



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.609375