July 5, 2011 -- Designing FPGA-based accelerators is a difficult and time-consuming task that can be eased by high-level synthesis Tools. To illustrate, we describe how a C-to-hardware methodology has been used to develop an efficient systolic array for the genomic sequence alignment problem. We also compare design performance with traditional HDL implementations.

FPGA gate density is doubling approximately every two years. Consequently, increasingly complex designs can be integrated into a single FPGA, which can now be considered as a high-power computing accelerator. However, pushing processing into such devices can lead to development time and design reliability issues. Recent efforts have helped FPGA-targeted application designers deal with large amounts of resources. In particular, electronic system level tools provide a higher level of abstraction than traditional HDL design flows. Several high-level languages (HLL) for modeling complex systems, and corresponding high-level synthesis (HLS) tools to translate HLL-based designs into HDL synthesizable projects are available. Most of them are based on a subset of C/C++ generally extended with specific types or I/O capabilities. Here we focus on the C to FPGA tool set and its associated flow.

By Alexandre Cornu, Steven Derrien, and Dominique Lavenier. (The authors are all with INRIA/ IRISA, Rennes, France.)