| Realizing the Promise of Electrically-Aware Custom IC Design | Publication: Electronic Design Magazine Contributor: Cadence Design Systems, Inc.
| | |
August 9, 2011 -- As silicon technology advances, a related increase in design complexity and uncertainty demands innovations in EDA solutions. The challenge for design teams is to improve productivity while differentiating their products. Uncertainty often results in scheduling constraints that may force a degree of overdesign. The result is conservative performance that may significantly reduce the value of moving to a new node. Increasing concerns about reliability (e.g., electromigration) produces additional uncertainty in physical design and is an inherent part of today's design flows.
Currently the schematic (electrical) and layout (physical) design processes are performed sequentially and there is little or no visibility into the electrical consequences of physical design decisions. It is only when the layout is complete that the physical design can be verified to meet the electrical intent of the designer. When verified behavior does not meet performance or reliability requirements, the design iterates between the layout and sign-off stages until such requirements are met.
Design teams have reported two to six major design iterations just to meet electromigration requirements alone. The layout changes to address the problem may not be apparent and additional iterations may be required to determine what to fix and how. Even when the fix is obvious, these modifications may influence other areas of the layout, making additional work necessary to meet the design intent.
While the uncertainty and lack of visibility reduces productivity, electrically aware design represents an opportunity for EDA companies to fundamentally change the custom design flow and directly enable product differentiation.
By David White and Michael McSherry. (White is senior architect in the Custom IC R&D Group at Cadence Design Systems, Inc. and McSherry is a software architect in the Custom IC R&D group at Cadence Design Systems.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Design Magazine website.
Read more about Cadence Design Systems, Inc. on SOCcentral.com |
| | Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, physical design, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, Cadence Design Systems, Electronic Design Magazine
| | 599/34463 8/9/2011 1021 141 | |
|
|
|
|
|
|
| | 0.15625 |
|
|
| Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054 | |
|
| | |
|
|
Subscribe to SOCcentral's SOC Explorer Newsletter and receive news, article, whitepaper, and product updates bi-weekly.
|
|
|
Exec Viewpoint
Reducing Power by Raising the Level of Abstraction
 David Pursley Director, Product Marketing Forte Design Systems
|
|
Exec Viewpoint
The Many Faces of Low-Power Verification
 Ghislain Kaiser CEO, Docea Power
|
|
Exec Viewpoint
Maximizing the Value of Your Internal IP
 Warren Savage CEO, IPextreme
|
|
|
|
Barbara's Bytes
So, Just What Is ESL?
 Barbara Tuck Senior Editor, SOCcentral
|
|
|
|
|
|
|
|
| Design Center |
| Whitepapers & App Notes |
|
|
|
|
|
| Live and Archived Webcasts |
|
|
|
|
|
| Newsletters |
|
|
|
|
|
|
About SOCcentral.com
Sponsorship/Advertising Information
|
|
|