September 15, 2011 -- Wirebond power bus planning is always impose challenge to designer with the consideration of performance budget (supply voltage), mask cost and power pin count.
For FPGA wirebond power bus planning, core power bus take serious hit compare to IO periphery region for few reason, power pad is located at the edge of the chip, type of bump pad architecture implementation, power to signal IO ratio, metallization budget. IO periphery though have the advantage of closer to power pad placement advantage, however to tight IO drop budget on DDR3 performance is none trivial task either.
In this article, we share the top 5 watch-outs for smoother wirebond power bus planning yet meeting the design performance,cost and power parameteric value. The discussion is based on traditional FPGA core wirebond power bus planning experience instead of new FPGA core full chip wirebond power bus planning methodology. However, the wirebond power bus watch-outs is applicable regardless of the FPGA wirebond power bus planning methodology.
Due to design complexity, fab process, technology node, and signoff PVT, some of the watch-outs may not impact other wirebond power bus planner but do hope the reader may benefit from this sharing.
By Lee Wei Ling and Ang Boon Chong. (Wei Ling and Boon Chong are with Altera Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
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