| Mentor Graphics Adds User Defined Fault Models and Cell-Aware ATPG to Improve IC Test Quality | | |
September 19, 2011 -- Mentor Graphics Corp. today announced new capabilities in the Tessent TestKompress and the Tessent FastScan tools that enable higher defect coverage and lower defect-per-million (DPM) levels for quality-critical applications such as military, medical, and automotive. User defined fault models (UDFM) and a new cell-aware ATPG flow together allow designers to target subtle shorts and open defects internal to standard cells that are not adequately detected with the standard stuck-at or transition-fault models.
"Cell-aware testing based on UDFM allows us to increase the quality of our manufacturing test by catching defects that would have gone undetected using conventional fault models," said Jeff Rearick, Senior Fellow at AMD. "Traditional fault models ensure that the periphery of standard cells and the interconnections between them are fully tested, but can miss some bridging or open defects internal to the cells. With the UDFM and cell-aware capabilities, TestKompress can generate patterns to specifically target these additional defects, giving us higher confidence in our production testing with minimal impact to test time. This takes us a big step closer to true zero-defect quality control."
Cell-aware fault models are generated using a one-time cell library characterization flow, which uses the Calibre extraction tools and the Mentor Eldo product for transistor-level fault simulation. Once characterization has been performed, the cell-internal fault models are automatically incorporated into TestKompress pattern generation using the new UDFM syntax. Cell library characterization is also available as a service from Mentor Consulting. In addition, designers can use the UDFM capability to define any proprietary fault model that may be needed to improve quality levels for their specific processes or applications.
"As we move to more advanced process nodes, we see a variety of new failure modes that must be addressed by IC testing," said Steve Pateras, Product Marketing Director at Mentor Graphics. "UDFM lets designers adapt to these new faults without waiting for commercial fault model libraries to catch up. "
Go to the Mentor Graphics Corp. website to find additional information.
| Read more about Mentor Graphics Corp. on SOCcentral.com |
| Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, automatic test pattern generation, ATPG, design for manufacturing, design-for-manufacturing, DFM, design for test, design-for-test, DFT, Mentor Graphics, Tessent TestKompress, Tessent FastScan,
| | 600/34665 9/19/2011 476 72 | |
|
|
|
| | 0.390625 |
|
|
| Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054 | |
|
| | |
|
|
Subscribe to SOCcentral's SOC Explorer Newsletter and receive news, article, whitepaper, and product updates bi-weekly.
|
|
|
Exec Viewpoint
Maximizing the Value of Your Internal IP
 Warren Savage CEO, IPextreme
|
|
Exec Viewpoint
Yes, Virginia, There Is a Stitch-and-Ship
 Dave Johnson VP of Sales Breker Verification
|
|
|
|
Barbara's Bytes
So, Just What Is ESL
 Barbara Tuck Senior Editor, SOCcentral
|
|
|
|
|
|
|
|
| Design Center |
| Whitepapers & App Notes |
|
|
|
|
|
| Live and Archived Webcasts |
|
|
|
|
|
| Newsletters |
|
|
|
|
|
|
About SOCcentral.com
Sponsorship/Advertising Information
|
|
|