September 26, 2011 -- ATopTech, Inc. announced today that NetLogic Microsystems, Inc. has selected ATopTech's Aprisa physical-design solution for designing complex system-on-chip (SOC) designs at 28nm. Aprisa will be used to design NetLogic Microsystems' next generation XLP II multicore processors.

"We chose ATopTech's Aprisa for our 28-nanometer tape-outs because it offers DRC-clean routed designs and timing-clean databases across multiple corners and modes. Aprisa's router was tailored to handle complex 28-nanometer design rules and its revamped timing engine offers good timing correlation with SI to our sign-off STA tool," said Nazar Zaidi, Vice President of Engineering at NetLogic Microsystems. "After successfully using Aprisa on our XLP832 multicore processor development in the 40-nanometer node, ATopTech was the clear choice for our future 28-nanometer designs."

NetLogic Microsystems' XLP832 multicore processor integrates 32 NXCPUs featuring quad-issue, quad-threaded and superscalar out-of-order capabilities. It contains a tri-level cache architecture providing a total of 12MBytes of cache, a high-performance memory subsystem with four on-chip 72-bit DDR3 memory controllers with 51.2Gbps of bandwidth, a low-latency, high-speed fast-messaging network and numerous autonomous-acceleration engines that off-load processing tasks from the processor core including a network acceleration engine, a packet ordering engine, a security engine, a compress/ decompression engine and an 8-channel DMA and storage-acceleration engine.

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