September 27, 2011 -- Synopsys, Inc. today announced availability of the latest release of its Synplify Pro and Synplify Premier FPGA synthesis tools. The new Synplify tool release lets engineers build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs). In addition, an enhanced interface for the tool lets designers track progress and analyze synthesis results hierarchically. For ASIC prototypers, support for Synopsys DesignWare Library MacroCell IP has been added, broadening DesignWare IP support and improving compatibility with Design Compiler.

"The enhancements in the latest release of Synopsys' Synplify synthesis software enable designers using our Stratix FPGAs to quickly complete their complex designs," said Phil Simpson, Senior Manager of Software Technical Marketing at Altera. "The combination of the Synplify Pro software with Altera's Quartus II place-and-route software and our high-performance FPGA families gives designers an easy way to quickly divide and conquer their complex systems. Synplify's enhanced hierarchical design flow, together with Quartus II incremental compilation feature, gives designers using our highest-density devices the ability to save hours per iteration by enabling quicker debug and validation of their designs while preserving parts of the design that are already known to work."

"Partnering with technology leaders like Synopsys enables us to deliver highly integrated design solutions," said Tom Feist, Senior Marketing Director, Design Methodology Marketing at Xilinx. "As Synopsys expands support for DesignWare, it enables designers prototyping SOCs to more easily integrate their key design functionality into their Xilinx devices. Engineers designing with our FPGAs will also find Synplify Premier software's hierarchical-design flow and advanced debug features improve their productivity in creating large-scale designs."

The 2011.09 Synplify software release gives designers the ability to create designs that are resistant to single-event upsets (SEUs) by including an option for designers to automatically preserve sequential logic. Synplify Premier software also automates implementation of 1-hot safe FSM error-detection circuitry, further increasing in-field system reliability of FPGA devices. To improve productivity in implementing large-scale designs, the new Synplify software release expands on the tools' hierarchical design-flow capability with a new GUI interface. The interface lets users intuitively validate and view synthesis settings prior to synthesis and then centrally monitor design progress hierarchically. Also, the latest Synplify software will automatically convert gated and generated clocks that cross hierarchical boundaries in an ASIC design into equivalent FPGA structures.

In addition, the latest release of Synplify Premier software now synthesizes encrypted DesignWare Library MacroCell Infrastructure IP. As a result, these encrypted RTL cores can now be read directly by Synopsys' FPGA and ASIC implementation tools in addition to verification tools, allowing ASIC designers to seamlessly prototype their ASIC designs in FPGAs. The newly supported DesignWare Infrastructure IP includes ARM AMBA 3 (AXI, AHB, APB) interconnect, APB advanced peripherals, APB peripherals, microcontrollers (DW8051, DW6811) and memory controller components.

"New features in the latest releases of Synplify Pro and Synplify Premier software enable FPGA designers to more easily pin-point design error sources throughout the design hierarchy while improving resistance to radiation effects during operation," said Ed Bard, Senior Director of Marketing of the Solutions Group at Synopsys. "This results in an overall lower cost of design through higher design productivity and fewer failures in the field."

Availability