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Atrenta Joins Cadence System Realization Alliance  
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October 24, 2011 -- Atrenta, Inc. has joined the Cadence Design Systems, Inc.'s Realization Alliance. The initial focus for the alliance will be to verify that output of the Cadence C-to-Silicon Compiler passes a set of high-level synthesis SpyGlass rules that will be jointly developed by Cadence and Atrenta.

The Cadence C-to-Silicon Compiler automatically generates synthesizable register transfer level (RTL) output starting from untimed C/ C++/ SystemC. Atrenta's SpyGlass is a widely used platform for validation and optimization of RTL descriptions prior to hand-off to physical design tools. Through this collaboration, Cadence and Atrenta will define a set of SpyGlass rules that verify C-to-Silicon output for parameters such as syntactic correctness, power, testability and clock synchronization. It is anticipated that the resultant rules will become part of C-to-Silicon internal testing, and a subset of these rules will also be available to end users.

Go to the Atrenta, Inc. website to find additional information.

E-mail Atrenta, Inc. for more information.

Read more about
Atrenta, Inc.
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Cadence Design Systems, Inc.
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, physical design, high-level synthesis, Atrenta, SpyGlass, Cadence Design Systems, C/C++, SystemC,
600/34945 10/24/2011 492 59


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