Design teams today struggle to meet current verification requirements for digital integrated circuits (ICs). Firstly, as Moore's Law continues to apply, designs are increasing exponentially in size and complexity. Moreover, the migration to nanometer process technologies at 130nm and below introduces additional electrical and physical effects that can dramatically impact IC performance. Nanometer effects such as increased capacitive coupling lead to crosstalk in both signal and clock nets, dictating increased emphasis on circuit-level analysis in timing verification.
For designers of leading-edge custom digital ICs, the movement to smaller nanometer sizes and faster clocks has introduced significant new challenges for design verification. According to a leading semiconductor manufacturer, the move from 180nm to 130nm causes 25X more nets to exhibit signal integrity problems. Traditional verification methods are unable to account for nanometer effects and providing needed accuracy, performance and capacity at the same time. Adding guard bands to deal with inaccuracy in traditional methods is not sufficient to address the design problem today. Significantly large guard bands slow down designs and performance requirements can not be easily met. Designers need a superior solution to meet their verification challenges.
Based on Nassda's production-proven verification technology, a new hybrid analysis combines dynamic and static methods to achieve SPICE-like accuracy in timing verification while delivering the exhaustive coverage and rapid performance of static methods. This hybrid approach lets engineers achieve accurate timing verification results needed to eliminate expensive silicon re-spins in complex nanometer custom digital designs. Although the hybrid technology is revolutionary, it is not disruptive. HANEX fits smoothly into today's design methodologies.