November 3, 2011 -- GOEPEL electronic GmbH has announced the availability of additional features in its TAPChecker EDA software for the generation of BSDL testbenches. The newly developed options extend the software's flexibility in terms of handling pin groups and complex port declarations for improved coverage of multi-chip modules and 3D chips. Users are now able to assign special vector sequences to complete port groups or to adopt complex bus structures into the simulation.

TAP Checker is based on modular platform architecture with a central database and individual licensed modules for data import/ export and automatic test vector generation. The software was designed for automatic testbench generation for simulations based on BSDL files as well as provision of test vectors for in-circuit testers. It can be utilized in various operating systems such as Solaris, Windows And LinuX, supporting the boundary scan standards IEEE 1149.1 and IEEE 1149.6.