November 2, 2011 -- OCP International Partnership (OCP-IP) today announced the availability of an enhanced version of its Transaction Generator (TG), which is a transaction-level (TL) SystemC simulator for benchmarking network-on-chips (NoCs) used in multi-processor system-on-chip (SOC) applications. The latest version now includes an Accurate Dynamic Random-Access Memory Model (ADM) package. The ADM is a configurable, transaction-level model for dynamic random-access memories (DRAMs). It considers the major delay parameters of real DRAMs and imitates their realistic timing behavior by capturing access dependencies.
The TG can generate traffic for network-on-chip according to abstract software and hardware workload models. Utilizing this tool makes simulation of larger systems substantially faster and the results obtained at this higher level can be accurately used in initial estimates when selecting and fine-tuning NoCs. During simulation, the TG measures performance metrics from the application and platform models, and from the traffic routed through network-on-chip. Because this freely available, highly-versatile tool, works at the transaction level, simulation of larger systems is substantially faster than those done at the clock-cycle accurate level.
The newly added DRAM executable can be used to test the delay and throughput of the memory subsystem for certain traffic flows. Integrated memory model enables two additional modeling features for TG: cache misses and shared-memory communication. Hence, the models can more accurately represent the performance of systems and enable a realistic evaluation of NoCs. The package also includes a basic set of nine traffic models from the multimedia and telecommunication domain.
The TG plus DRAM models are now freely available to both OCP-IP members and non-members alike through GNU LGPL, and is an ideal addition to all system-level designers evaluating various interconnection solutions in a simulation model of a real, complex system. It can also be used to simulate IP blocks before real implementations are available which enables the design of interconnect and implementation of IP blocks and SW for processors to advance in parallel, saving time, resources, and ensuring a faster time-to-market.
"The work on this Transaction Generator and DRAM package by our Network on Chip Working Group showcases co-operation and collaboration among both our industry and academic researchers, ensuring synergy advantages in the field of NoCs," said Ian Mackintosh, President and Chairman of OCP-IP.
The Transaction Generator and DRAM model kit were developed by Tampere University of Technology and Royal Institute of Technology (KTH) in conjunction with members of OCP-IP's Network on Chip Benchmarking working group including: Boston University, University of British Columbia, Carnegie Melon University, Washington State University, and Transylvania University in cooperation with industry members of the OCP-IP.
The Network on Chip Benchmarking Working Group has also issued an open call for Benchmarks to be distributed to researchers. NoC researchers may submit benchmarks from any application domain to be included. For more information on the call for benchmarks, go to www.ocpip.org/ocpspec_call_for_benchmarks.php
Go to the OCP International Partnership (OCP-IP) website for details.