November 23, 2011 Multi-processor system-on-chip (MPSoC) is a growing industry; studies predict the use of hundreds of processors in one system. However, the impact of targeted device internal structure on the implementation of such systems has not been studied thoroughly. We developed a a network-on-chip (NoC) with mesh-of-trees topology that has been proposed in literature.
This particular topology is implemented into two different FPGA devices: the Xilinx Virtex4 and the AboundLogic Raptor 750. The Raptor FPGA has a mesh-of-trees as routing interconnect structure, while the Virtex 4 routing is based on a Manhattan structure. Our article examines the potential benefits of the correspondence in topology of logical and physical interconnect. Results shows an important boost in performance level but less gain in resources usage.
By Mazen Khaddour and Omar Hammami. (Khaddour and Hammami are with ENSTA-ParisTech.)
This brief introduction has been excerpted from the original copyrighted article.
