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Building 3D-ICs: Tool Flow and Design Software - Part 1  
Publication: EE Times EDA Designline
Contributor: Tezzaron Semiconductor
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November 14, 2011 -- The industry's current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D tool flows, thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D design. A new 3D design process is evolving gradually from that 2D heritage. When Tezzaron designed its first 3D circuits in 2003, the designers used standard 2D CAD tools and cobbled together a 3D DRC and LVS flow based on scripts. Today there are tools to handle a complete backend flow and strides are being made to enable true 3D design partitioning, synthesis, placement, and routing.

By Robert Patti. (Patti is CTO and Vice President of Design Engineering of Tezzaron Semiconductor (Singapore) Pte, Ltd.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Tezzaron Semiconductor
on SOCcentral.com

Keywords: ASICs, ASIC design, 3D ICs, 3D chips, stacked ICs, packages, packaging, EDA, EDA tools, electronic design automation, Tezzaron Semiconductor, EE Times EDA Designline
599/36207 11/14/2011 583 78
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