December 7, 2011 -- Scaling down CMOS technologies to 40nm and below is imposing new challenges for physical-design engineers relating to timing closure in their designs. In higher technology (90nm and above), process, voltage and temperature (PVT) corners with the highest temperatures used to be the worst locations for synthesis.
By Rajiv Mittal, Hans Jain, Gaurav Goyal, and Abhishek Mahajan. (The authors are all with Freescale Semiconductor, Inc.)
This brief introduction has been excerpted from the original copyrighted article.