February 22, 2012 -- The standard for Wide I/O mobile DRAM, released by Jedec in January, uses through-silicon vias (TSVs) to connect DRAM to logic on three-dimensional integrated circuits. With its 512-bit data interface, JESD229 Wide I/O Single Data Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.
Devices that use TSV connections between homogeneous dice are already available. Wide I/O is leading the way to TSV connections between heterogeneous dice.
Among the companies offering devices with homogeneous TSV connections are Xilinx, whose Virtex-7 2000T field-programmable gate arrays use logic connected to logic, and Samsung, whose 32-Gbyte registered dual-in-line memory modules (RDIMMs) use DRAM stacked with DRAM. There are many good reasons for homogeneous TSV connections. Xilinx claims its devices offer a hundredfold improvement in die-to-die connectivity bandwidth per watt with one-fifth the latency; Samsung claims a 40 percent reduction in power.
Even a device that has twice as many cells on it than the dice we can produce today can use TSVs to connect two homogeneous dice. But what happens when a device has more types of different cells than the dice we can produce today?
The full potential of TSV technology comes with the ability to connect dice with different physical properties. Though it is possible to put logic, memory, radio-frequency (RF), analog, power, and image-sensing circuits all on the same piece of silicon, it may be preferable to put them on separate dice for the best performance at the lowest cost.
By Marc Greenberg and Samta Bansal. (Greenberg is Director of Product Marketing for the SoC Realization Group at Cadence Design Systems, Inc. Bansal is Senior Manager of Product Marketing for the SoC Realization Group at Cadence.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
Read more about
Cadence Design Systems, Inc.