March 5, 2012 -- Cadence Design Systems, Inc. today introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest 20-nm technology node. Developed in close collaboration with leading IP and foundry partners and customers, the new RTL-to-GDSII design, implementation and sign-off flow enables more efficient development of SOCs, meeting and exceeding the power, performance and area demands of today's market requirements.
The new RTL-to-GDSII flow is enabled by Encounter RTL Compiler, Encounter Test, Encounter ECO Designer, Encounter Digital Implementation System, Clock Concurrent Optimization (CCOpt), Encounter Timing System, Encounter Power System, Cadence QRC Extraction, Cadence Physical Verification System, and design for manufacturing technologies.
"The Cadence Encounter RTL-to-GDSII flow enabled us to achieve the chip performance and feature objectives of our 1-GHz ARM Cortex-A5 processor-based smartphone platform on time and with greater development efficiency," said Dr. Leo Li, president and CEO of Spreadtrum. "The new flow, with features such as physical-aware synthesis and the GigaOpt engine, enables excellent power-performance-area trade-offs that support the development objectives for our complex designs at advanced process nodes. The 3G low-cost smartphone market in China is expected to experience ongoing rapid growth, and our smartphone platform is now well positioned to capture this market opportunity."
The new Encounter 20-nm methodology delivers silicon-proven 20-nm capabilities with correct-by-construction double-patterning support, covering capabilities from floorplanning, placement and routing to sign-off timing, power and physical verification. This approach improves die area efficiency of 20-nm double-patterning designs, and enables more efficient engineering change order (ECO) revisions. Enhancements to the Cadence Physical Verification System provide foundry-qualified 20-nm in-design checking and final sign-off verification to ensure DRC and double patterning color correctness.
This latest release of the Encounter RTL-to-GDSII flow also includes the new GigaOpt engine, which integrates key physical-aware synthesis technology with physical optimization, enabling faster timing closure and better correlated results. It is a scalable optimization engine that supports designs featuring leading high-performance processors. By harnessing the power of multiple CPUs, the engine produces results much faster than traditional optimization engines. In addition, the new differentiated CCOpt technology unifies clock tree synthesis with physical optimization, resulting in up to 10% improvement in design performance, and up to 30% reduction in clock tree power and area.
Another key element of the release is GigaFlex technology, a new capability that greatly expands the capacity to handle today's largest designs of 100 million instances or more. Designers can now achieve full-chip design prototyping goals in just 10% of the time required previously, enabling them to uncover potential issues earlier to produce the optimal design floorplan sooner. The GigaFlex technology enables concurrent top-and-block hierarchical design and implementation, reducing iterations and total design cycle time by an order of magnitude. In addition, automated functional ECO technologies accelerate pre- and post-mask ECO changes, which are reduced to hours or days through smart hierarchical design handling.
Go to the Cadence Design Systems, Inc. website to find additional information.