March 26, 2012 -- Avery Design Systems, Inc. has announced availability of its DDR-Xactor verification IP providing DDR and LPDDR memory models and a complete DFI-PHY verification solution. Models and compliance test suites are developed in SystemVerilog and support UVM, OVM, and VMM environments.

DDR-Xactor VIP includes:

SDRAM memory chip and DIMM models. DFI-PHY model. Simple AXI-based memory controller model. Compliance testsuite. Timing and protocol checks. DFI and JEDEC protocol analyzer trackers.

The memory models support all speed modes and configurations including parameter files for the major SDRAM vendors including Samsung, Hynix, Micron, and Elpida. Memory models support a full SDRAM/DIMM user API with many advanced features not included in many "free" models such as:

Clock jitter. Random DQS timing. CRC/parity error injection. Backdoor access to DDR chip and DIMM memory locations. Callbacks and analysis ports for memory access and state transitions .

DFI-compliant PHY verification is performed using the Avery provided plug-and-play testbench and compliance testsuite focusing on DFI functional requirements such as reset, write leveling, refresh, power down, frequency change, and PHY update.

SOC/ memory controller verification is performed using the Avery DDR chip/ DIMM memory models to test memory controller functions such as memory refresh and control modes such as DDR4's PDA and modereg readout.