December 1, 2003 -- One of the key factors in the design and development of submicron chip designs is the setting of good physical and timing constraints, no matter what type of design methodology you use. Constraints are especially important in hierarchical design, where good block constraints improve your ability to implement the blocks separately and then achieve overall timing closure efficiently. This article provides insight into the nature of constraints and descriptions of best practices for managing constraints in hierarchical design flows.
By Vijay Gullapalli. (Gullapalli is currently a Senior Design Consultant with Synopsys Professional Services.)
This brief introduction has been excerpted from the original copyrighted article.