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Ensuring Successful Third-Party Intellectual Property Integration  
Publication: EE Times EDA Designline
Contributor: Open-Silicon, Inc.
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March 26, 2012 -- Today's complex ASICs often leverage open-market IP to take advantage of reuse of standard functional blocks, and thereby improve time-to-market and development efficiency. However, the integration of that third-party IP, if done poorly, can lead to painful cost overruns and schedule delays. To ensure proper IP core integration, Open-Silicon has developed a detailed and comprehensive process involving close collaboration with IP partners and the SOC design team. This article will illustrate this process by showing how Open-Silicon and Kilopass worked together on a recent project to ensure success.

At the highest level, Open-Silicon employs a four-step process to ensure that the IP included in its design will achieve first-time silicon success. These steps include IP selection, IP procurement, IP qualification and IP integration.

By Mohit Gupta and Bernd Stamme. (Gupta is an IP manager with Open-Silicon, Inc. and Stamme is Director for Marketing and Applications at Kilopass Technology, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Open-Silicon, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, IP, intellectual property, cores, Open-Silicon, EE Times EDA Designline
602/38193 3/26/2012 902 92


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