April 10, 2012 -- Cadence Design Systems, Inc. announced today that China's Semiconductor Manufacturing International Corp. (SMIC) has introduced a low-power, advanced-node IC design reference flow using Cadence digital technology and SMIC's 40-nm manufacturing process. This new reference flow offers design teams a predictable and accelerated path to complex SOC designs for a wide range of low-power applications, including the latest consumer electronics products such as tablets and smartphones.

The SMIC-Cadence flow automates designs with advanced power-management features. This production-proven methodology is fully incorporated across the complete and integrated Cadence RTL-to-GDSII flow, which includes Encounter RTL Compiler, Encounter Conformal Low Power, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, Cadence QRC, Cadence CMP Predictor and Cadence Physical Verification System.

"We have worked closely with Cadence to develop a reference flow that helps our customers accelerate and differentiate their low-power, high-performance chips," said Tianshen Tang, Vice President of SMIC Design Service. "By using this interoperable, low-power, Common Power Format-based flow from RTL to GDSII, design teams can achieve faster time-to-volume for advanced low-power 40-nanometer designs."