March 21, 2012 -- Floorplanning is among the most crucial steps in the design of a complex system-on-chip (SOC), as it represents the trade-offs between marketing objectives and the realities of silicon at the targeted process geometry. We begin by describing the impact on Moore's Law of successive generations of silicon design. Then, we will detail the opportunities that next-generation silicon provides to marketing in creating the functionality of a new design.
An explanation of the growing need to implement security in next-generation SOC designs follows. Next, the discussion details the trade-offs the design architect makes to accommodate large third-party intellectual property (IP) blocks, including memory. It concludes with a description of the give and take between adding peripherals to the SOC and the impact on the SOC's I/O pads and silicon area.
By Andre Hassan. (Hassan is the Field Marketing and Applications Director at Kilopass Technology, Inc.)
This brief introduction has been excerpted from the original copyrighted article.