April 6, 2012 -- Writing power intent for a design using the IEEE 1801 Unified Power Format (UPF) is generally an easy and straight-forward task. If the design will be optimized in a flat fashion (e.g., the entire design is optimized top-down in a single session), then writing the power intent is fairly simple.
Situations such as being too rigid in where your power management cells need to be implemented and writing power intent for hierarchical designs can make writing UPF a much more difficult task. This article details the considerations that you need to take into account when writing UPF for a hierarchical design methodology.
By Jeffrey Lee and Mary Ann White. (Lee is a staff corporate application engineer for Synopsys, Inc.'s Power Compiler. White is the Product Marketing Director for Galaxy low-power implementation products at Synopsys)
This brief introduction has been excerpted from the original copyrighted article.
Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, power analysis, power optimization, low power design, low-power design, Unified Power Format, UPF, Synopsys, EE Times EDA Designline
