Page loading . . .

  
 You are at: The item(s) you requested.Saturday, May 25, 2013
JEDEC Announces Plans to Standardize Non-Volatile Wireless Memory  
 Printer friendly
 E-Mail Item URL

April 16, 2012 -- JEDEC (Solid State Technology Association) has announced that its JC-64 Committee for Embedded Memory Storage and Removable Memory Cards has formed a Subcommittee focused on the standardization of non-volatile wireless memory. To be chaired by Nokia and vice-chaired by Micron Technology and Samsung Semiconductor, the JC-64.9 Subcommittee for Wireless Memory welcomes interested companies worldwide to participate by joining JEDEC.

Wireless memory is rapidly emerging as the next generation in data-transfer technology, and is intended to enable fast, wireless connectivity with read/ write capability between mobile devices (Wireless Memory Hosts) and battery-free memory tags (Wireless Memory Tags). "There is currently no standard for this type of high speed, low power wireless data transfer," said Hannu Kauppinen, Head of Nokia Research Center. "Creating a standard is essential to enabling manufacturing, distribution and retail businesses to benefit from the 100+ Mbit/s transfer rates achieved at close proximity, using very low power wireless memory. It will also enable consumers to enjoy new, fast wireless experiences, such as downloading a music album in under 10 seconds in a store."

"We are confident about our capability for providing wireless mobile applications with more effective storage memory solutions that will enable businesses to have greater flexibility in accommodating new digital applications," said Jim Elliott, Vice President, Memory Marketing and Product Planning, Samsung Semiconductor, Inc. "In capitalizing on the market’s rapid adoption of wireless applications, this soon-to-be-standardized technology offers multiple alternatives for sharing and storing content wirelessly, including device-to-device and device-to-accessory connectivity."

"Wireless memory technology at these capacities will enable innovative use cases to transfer contents to/from mobile devices," said Micron Senior Director for Wireless Solutions Group R&D, Marco Dallabora. "Standardization activities will focus to create a solution which is memory interface agnostic with respect to the actual structure of the Wireless Memory Tag and Wireless Memory Host."

John Kelly, JEDEC President, added, "The new wireless memory activity in JC-64 is part of an ongoing effort within JEDEC to extend memory technologies to meet the industry's need for innovative solutions that best meet enterprise and consumer demands. We welcome all interested companies to participate in the development of open industry standards within JEDEC to help enable and grow the market for wireless memory."



Go to the JEDEC website to find additional information.

Read more about
JEDEC
on SOCcentral.com


Keywords: computer system design, general-purpose computers, special-purpose computers, embedded system design, embedded systems, nonvolatile memory, non-volatile memory, NVM, wireless, JEDEC (Solid State Technology Association)
601/38255 4/16/2012 255 51


Designer's Mall
0.453125



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.5