April 16, 2012 -- ARM today announced the availability of a significantly expanded lineup of ARM Processor Optimization Pack (POP) solutions for TSMC 40-nm and 28-nm process technologies targeting a range of ARM Cortex processors. At least nine new POP configurations targeting Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores will be released.

An essential element of ARM's comprehensive implementation strategy, POPs enable ARM partners to quickly close timing of single-, dual- and quad-core implementations across a broad envelope of power, performance and area optimization points. This solution reduces risk and improves time-to-market in the development of Cortex processor-based systems-on-chip (SOCs) with partners achieving competitive results in as little as six weeks.

At the leading-edge 28-nm HPM (high performance for mobile) and 28-nm HP (high performance) process variants, ARM is launching new POPs for the Cortex-A9 core as well as the first POPs for ARM's newest Cortex-A7 and Cortex-A15 processors. Since the Cortex-A7 and Cortex-A15 cores are used in tandem as ARM's big.LITTLE energy-efficient processing solution, the addition of POPs for both cores assures a complete solution for big.LITTLE implementations. ARM's lead licensee for the Cortex-A15 POP for TSMC 28-nm HPM is progressing toward the tape-out of its first chip in the coming months.

At TSMC 40-nm LP (low power), ARM's existing POP offering for the Cortex-A5 and Cortex-A9 processors is being augmented with the new Cortex-A7 POP. In addition, working in concert with TSMC, ARM will offer new POP variants supporting the latest high-speed options for TSMC 40-nm LP, so those process options can take full advantage of the POP implementation benefits. ARM's POPs for TSMC 40-nm LP for Cortex-A5 (1.0GHz) and Cortex-A9 (1.4GHz) are shipping in production chips by ARM partners in such applications as smart-TV, set-top box, mobile computing and smart phones.

A Processor Optimization Pack solution is composed of three elements necessary to achieve an optimized ARM core implementation. First, it contains ARM Artisan physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology. This physical IP is developed through a tightly coupled collaboration with ARM processor engineers in an iterative process to identify the optimal results. Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation. Finally, it includes a POP Implementation Guide that details the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.

"A single POP product can be applied to energy-efficient mobile, networking or even enterprise applications, providing a wide range of flexibility for ARM SoC partners to optimize performance and energy-efficiency while reducing risk in their designs," said Simon Segars, Executive Vice President and General Manager, Processor and Physical IP Division, ARM. "Only ARM can offer a complete roadmap of Processor Optimization Pack implementation solutions so deeply integrated and tightly aligned with ARM processor development activities now and into the future."

The summary below describes the existing and newly announced POP products for TSMC processes. ARM also incorporates the POP optimizations in hard macros of Cortex cores.

POP availability by process technology