Page loading . . .

  
 You are at: The item(s) you requested.Wednesday, May 22, 2013
Xilinx Display Targeted Design Platform Accelerates Development of 4K2K Displays  
 Printer friendly
 E-Mail Item URL

April 16, 2012 -- Xilinx, Inc. today announced at the National Association of Broadcasters Show (NAB) availability of the Display Targeted Design Platform (TDP) based on the ACDC (acquisition, contribution, distribution and consumption) 1.0 hardware platform from Premier Xilinx Alliance Program member Tokyo Electron Device, Ltd. (TED).

The Display TDP accelerates development of 4K2K monitors and high-resolution projection systems by stitching together existing 1080i or 1080p video sources into virtually seamless 4K displays. It's the latest addition to Xilinx's growing library of TDPs that allow broadcast equipment designers and manufacturers to quickly implement solutions targeting the acquisition, contribution, distribution and consumption (ACDC) areas of the video production value chain.

The Display TDP is built around Xilinx's Kintex-7 family of FPGA devices built on 28-nm technology. Broadcast equipment designers who base new equipment designs on the Kintex-7 FPGA-based Display TDP will be able to reduce power consumption, increase their system performance to 4K2K resolution and accelerate their design productivity to rapidly implement a working display or projector system. The inherent programmability of FPGAs enables flexible adaptation throughout design and into production to meet ever evolving content delivery and display standards. By using the Display TDP, designers can focus on features that will differentiate their products and get to market more quickly.

"Kintex-7 devices are the first FPGAs to bring high-speed serial performance, crucial to supporting new display interfaces, at a price point that fits within the power and system-performance requirements necessary to produce high-end 4K2K displays, projectors and consumer digital televisions," said Yasuo Hatsumi, Vice President at TED. "By combining Xilinx's display reference designs with our hardware platforms, designers can avoid the cycles necessary to develop a video system framework from scratch."

Display Targeted Design Platform

The new Kintex-7 FPGA-based Display TDP offers integrated productivity improvements for developers of super-high-resolution visual display systems that lets them seamlessly stitch together four 1920x1080 interlaced or progressive video input channels to develop 4K2K displays, digital cinema/ home theatre projectors or broadcast studio monitors. The TDP includes three reference designs: an HD-to-4K2K scalar/ upconverter, Four HD input mosaic, and 4K2K frame-rate converter (FRC) 60Hz to 120Hz.

Availability

The ACDC 1.0 baseboard with the Kintex-7 FPGA as well as the targeted reference designs will be available in Q2 2012. For information on the Kintex-7 FPGA Display Kits, which include the ACDC 1.0 baseboard and several interface-specific FMC cards supporting HDMI, SDI, LDVS, and V-by-One HS, visit www.xilinx.com/display.



Go to the Xilinx, Inc. website to find additional information.

Read more about
Xilinx, Inc.
and
Tokyo Electron Device, Ltd.
on SOCcentral.com


Keywords: FPGAs, field programmable gate arrays, FPGA design, video processing, Xilinx, Tokyo Electron Device,
601/38265 4/16/2012 274 50


Designer's Mall
0.40625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.484375