| Solido Announces High-Sigma Monte Carlo Meta-Simulator | | |
April 24, 2012 -- Solido Design Automation, Inc. formally announced today its High-Sigma Monte Carlo (HSMC) meta-simulator solution. Solido's HSMC, part of the Variation Designer product family, was released in October 2010 and is in use at 7 of the top 20 semiconductor vendors. It provides accurate, scalable and verifiable analysis and design solutions for memory chips, and is more than 100 times faster than Monte Carlo analysis.
Meta-simulation has historically been limited to simplistic methods, such as running corners or running Monte Carlo. Today, meta-simulation techniques can be much more powerful, addressing designer challenges and speeding up different analyses types in precisely-targeted ways. For example, rather than running 100 or 10,000 PVT corners just to search for the worst cases, a "Fast PVT" meta-simulator would analyze all the PVT corners and intelligently simulate only the small subset requires to identify the worst-case corners with confidence.
Meta-simulation goes beyond distributed processing; it also adds efficiency to high-value analysis capabilities such as: fast PVT analysis; fast extraction of statistical corners; and fast sensitivity analysis. An ideal meta-simulator for memory design measures yield-performance trade-offs out to 5 and 6 sigma, with the same accuracy as millions or billions of Monte Carlo simulations, but with 100X+ fewer simulations.
Solido's High-Sigma Monte Carlo key features for memory design
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Achieves high-sigma memory verification in thousands rather than millions or billions of simulations. It analyzes the billions of Monte Carlo samples, and then focuses its Spice simulation resources to find rare failures or validating the target yield.
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Runs fast enough to facilitate both iterative design and verification within production timelines, enabling yield-performance trade-offs. A Solido HSMC 5 billion Monte Carlo sample run can take as little as 15 minutes.
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Provides Spice-accurate information in the extreme tails of the high-sigma distribution, where defects are expected to occur. Is applicable to production-scale high-sigma designs with hundreds of process variables.
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Interfaces to all the leading Spice simulators used by memory designers. Runs at the command-line, just like a single simulation, while supporting parallelization to hundreds of cores/machines, managing multiple simulations through LSF/SGE.
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Analyzes design sensitivities to variation, presents design opportunities to shrink memory area, power and improve performance, and provides integrated results verification.
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Go to the Solido Design Automation, Inc. website to find additional information.
| E-mail Solido Design Automation, Inc. for more information.
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Solido Design Automation, Inc.
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| Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, Monte Carlo simulation, simulators, Solido Design Automation,
| | 601/38302 4/24/2012 268 49 | |
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