April 24, 2012 -- Xilinx, Inc. has announced the Vivado Design Suite, a new IP and system-centric design environment built from the ground up to accelerate design productivity for the next decade of "all programmable" devices.Vivado tools not only speed the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM processing systems, analog mixed-signal (AMS), and a significant percentage of semiconductor intellectual property (IP) cores.
"Vivado tools are the culmination of work started by Xilinx engineers in 2008 in response to customers' needs for more productivity, faster time-to-market, and the ability to go beyond programmable logic to programmable systems integration. It has been beta-tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using our stacked-silicon interconnect-based Virtex-7 devices for extreme capacity and bandwidth," said Victor Peng, Xilinx Senior Vice President of Platforms Development.
About the Vivado design environment
The Vivado Design Suite provides a highly integrated design environment (IDE) with a completely new generation of system-to-IC level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the user's needs. Xilinx architected Vivado tools to enable the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.
To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards-based packaging of both algorithmic and RTL IP for reuse; standards-based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.
To address implementation bottlenecks, Vivado tools include a hierarchical device editor and floorplanner, a 3X to 15X faster logic synthesis tool with industry-leading support for SystemVerilog, and a 4X faster, more deterministic place-and-route engine that uses analytics to minimize a "cost! function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. Finally, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.
The version 2012.1 is available as part of an early access program. Potential customers should contact their local Xilinx representative. Public access will commence with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 extensible processing platform (EPP) support later in the year. ISE Design Suite Edition users with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost. The ISE Design Suite will continue to be supported by Xilinx for customers targeting 7 series devices and prior generations.
Go to the Xilinx, Inc. website to find additional information.