April 27, 2012 -- Designing reliable three-dimensional (3D) system-on-chips (SOCs) is extremely complex, and critical for the next level of integration in silicon design. In a 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by through-silicon-vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits.

By Vinayakam Subramanian and Jairam Sukumar. (Subramanian is a lead applications engineer at Apache Design Solutions, Inc. and Sukumar is a Member of Technical Staff at Texas Instruments, Inc.)