April 20, 2012 -- Power is a daunting challenge for modern system-on-chip (SOC) designs, from both the power-consumption and power-integrity perspectives. Achieving low power, from mobile and wireless designs to consumer devices to high-performance networking and computing applications that face power supply and cooling limitations, is now critical to design success.At the same time, rising complexity and chip-level power-management techniques make power-integrity analysis from chip-to-package-to-system essential. Designing for low power and power integrity is not automatic; there is no "low-power" button.
This article describes a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off.
By William Ruby. (Ruby is the Senior Director of Product Engineering for RTL Power products at Apache Design Solutions, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, power analysis, power optimization, power integrity, power management, Apache Design Solutions, EE Times EDA Designline
