April 30, 2012 -- Cadence Design Systems, Inc. today announced TripleCheck IP Validator, a new addition to the Cadence verification IP (VIP) catalog that simplifies and accelerates compliance testing of interface-design IP, such as PCI Express.

The growing complexity of standard interfaces, typified by high-speed interconnects such as the PCI Express 3.0 standard and cache-coherent SOC fabrics such as AMBA 4 AXI Coherency Extensions (ACE), make them increasingly difficult to verify. TripleCheck IP Validator addresses this issue by building on the earlier generations of Cadence compliance solutions: PureSuite and Compliance Management System (CMS). TripleCheck combines features of both solutions plus significant new capabilities.

"Feedback from hundreds of users over several years was used to shape TripleCheck," said Erik Panu, Vice President of Research and Development for Verification IP, System and Software Realization Group, Cadence. "Customers wanted the extensive directed tests that PureSuite provided, plus the constrained-random testing approach of CMS and vPlan, an interactive verification specification that correlates coverage from regression runs to the protocol specification, all based on the Universal Verification Methodology (UVM)."

Availability and compatibility

IP Validator is currently available for PCIe Gen 3, and Cadence has support for several additional protocols in development for release later this year. Its test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading testbench languages.