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Wednesday, June 19, 2013

PLDA Introduces QuickTCP, a Full Hardware 10G TCP/IP Stack IP Core for FPGAs

May 3, 2012 -- PLDA today unveiled its 10Gb TCP/IP hardware stack IP core. PLDA's QuickTCP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. QuickTCP features an industry-standard AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. Designed with performance in mind, QuickTCP IP provides extremely low latency of less than 150ns to the FPGA fabric, and its scalable architecture provides a seamless migration path to 40G and beyond.

In addition, when combined with the PLDA QuickPCIe advanced AXI4 based PCI Express Gen3 with DMA IP core and its latency-optimized Linux device driver, the resulting solution offers outstanding value for those in the data-intensive financial and networking spaces, with demonstrated 10G wire to user space latency under 1.5µs.

QuickTCP key features

Full RTL layers 2, 3, 4 implementation.
Integrated layer 1 PHY interface for Altera Stratix IV, Stratix V and Xilinx Virtex-7, Kintex-7.
Supports Client and Server mode.
Supports up to 16 TCP sessions, easily scalable to 64 sessions or more.
Easy to use standard-based user interface (AXI Streaming/ AXI Lite).
Integrated TCP Options Management (MSS, window scaling, timestamps) and flexible management interface
Hardened ICMP and ARP.
Standard MTU (1500 and 9000).
VLAN configurable at run-time.
Fully configurable Retry memory (internal or external DDR/QDR/RLDRAM).

Availability

The PLDA QuickTCP IP is available now from PLDA. For a risk-free, free of charge evaluation, visit the PLDA website.

Go to the PLDA website to find additional information.

E-mail PLDA for more information.

Read more about
PLDA
on SOCcentral.com

Keywords: FPGAs, field programmable gate arrays, FPGA design, TCP/IP Stack IP, intellectual property, cores, PLDA, QuickTCP,

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