May 14, 2012 -- Sigrity, Inc. today introduced XcitePI IO Interconnect Model Extraction as part of its comprehensive suite of high-speed analysis software products. The technology generates precise chip I/O power/ ground and signal-interconnect models for accurate system-level analysis of high-speed channels and buses.Unique built-in IO quality assessment capabilities let designers quickly check I/O power/ ground robustness and signal electrical performance to identify potential design defects.
According to Sigrity President Dr. Jiayuan Fang, simultaneous switching output (SSO) analysis has been either unduly pessimistic or overly optimistic. The lack of I/O interconnect models made the simulated power/ ground noise at driver and receiver sides unpredictable, especially when a large number of drivers switch simultaneously. "Accurate models of chip I/O interconnects that fully represent the distributed nature of power, ground and signals as well as their electromagnetic coupling effects were not available in commercial EDA flows," he said. "XcitePI IO Interconnect Model Extraction fills this gap and builds on Sigrity's capability to provide the accuracy and efficiency needed to model and simulate chip-to-chip signal and power integrity for today’s challenging high-speed designs."
The chip I/O models created by XcitePI IO Interconnect Model Extraction offer both high resolution and compact size to ensure accuracy and efficiency. These models can be used in conjunction with Spice-compatible circuits for system-level simulations. Taking chip layout data in GDSII or LEF/DEF formats, the XcitePI IO Interconnect Model Extraction tool generates a Spice netlist that consists of a fully distributed I/O power/ ground model and I/O signal connections from I/O cells to bumps. It accounts for all coupling between the power, ground and signals on the chip, the distributed capacitance associated with the power and ground systems, and on-chip decoupling capacitors connected to the power and ground systems.
The resulting chip I/O interconnect model includes external terminals on the bump side with Sigrity's Model Connection Protocol (MCP) header information for easy connection to IC package models. Similarly, the model includes external terminals at the I/O cell level to streamline connection with targeted driver/ receiver models. Thus, XcitePI IO Interconnect Model Extraction provides precise interconnect models for chips, packages and boards.
The Sigrity XcitePI IO Interconnect Model Extraction tool also enables quick assessment of power and ground quality along with signal performance at every I/O cell. Graphical representations of electrical performance at each cell help users quickly identify weak or problematic physical areas and perform what-if analysis to rapidly improve the design.
XcitePI IO Interconnect Model Extraction is part of Sigrity's XcitePI chip-level analysis family that supports both pre- and post-layout design improvement. XcitePI applications enable both transient and frequency domain simulations of the full-chip power delivery network and take IC package effects into account; they also facilitate chip-level what-if analysis to evaluate decoupling capacitor placement along with the impact of power grid and bump design changes. A unique XcitePI planning module enables chip-level studies to begin early.
Availability and Pricing
XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms with pricing starting at $108,000 for a 3-year license.
Go to the Sigrity, Inc. website to find additional information.