May 7, 2012 -- The design and implementation process for integrated circuits has been honed and perfected for decades by the design and the EDA community. However, the reliability-verification process has been slow to catch up, especially due to the complex nature of failure mechanisms. Chip designers in the past were willing to take risks when it came to reliability verification because it was not seen as a functional failure or something that caused yield fallout.
But times have changed and the EDA and simulation software community has swiftly responded to the needs of a simulation-driven reliability analysis model. This article will delve into what it takes to design for reliability today.
By Arvind Shanmugavel. (Shanmugavel is Director of Applications Engineering at Apache Design Solutions, Inc.)
This brief introduction has been excerpted from the original copyrighted article.