| Interconnect Modeling at 20nm: More of the Same or Completely Different? | Publication: Electronic Engineering Times (EE Times) Contributor: Mentor Graphics Corp.
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May 10, 2012 -- Whether you are migrating to 20-nm processes, considering the migration, or just watching the fireworks, you no doubt understand that there are profound issues to consider for physical design and implementation. Double-patterning (DP) is driving new design requirements, and if you've been following any of the industry discussion, you know that words such as coloring, colorless, cutting, stitching, and anchoring are now part of the vocabulary for 20-nm design.
With 20nm and DP, we have geometries on the same layer being produced by different masks. This shift in silicon manufacturing changes the requirements for physical design; which means design methodologies, design tools, and verification tools must evolve to ensure we can continue producing robust designs within these new constraints.
By Carey Robertson. (Robertson is a Director of Product Marketing at Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.
Read more about Mentor Graphics Corp. on SOCcentral.com |
| | Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, on-chip interconnect, network-on-chip, NoC, Mentor Graphics, Electronic Engineering Times (EE Times)
| | 602/38447 5/10/2012 574 92 | |
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| | 0.171875 |
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