May 14, 2012 -- ICScape, Inc. today announced the global availability of its EDA solutions that accelerate design closure. The products are silicon-proven, offering scalability, high value and enabling up to 50% reduction in time-to-closure.
ICScape's design-closure solutions
TimingExplorer, a physically-aware timing ECO tool.
ClockExplorer, which automates complex SOC clock analysis and optimization.
Skipper, a high-capacity and ultra-fast integrated chip finishing solution.
FlashLVL, the fastest layout versus layout comparison (XOR) tool.
ICScape, by virtue of its merger with Huada Empyrean Software (HES) in China, has added HES' analog/ mixed-signal product line to its suite. They are, Aether (OpenAccess-based custom IC design platform, schematic and layout editors), Aeolus (circuit simulator), iWave (waveform viewing and analysis), Argus (physical verification), PVE (physical verification debugger) and RCExplorer (RC extraction and analysis that can be used in all design stages).
Yu Xia, Senior Manager in Physical Design, from HiSilicon said, "Practically speaking, every SOC design closure takes not only a significant amount of time and effort, but multiple iterations as well. Using ICScape's physically-aware timing tools, and Skipper, its chip-finishing capability, we reduced the number of iterations by at least 50 percent on each SOC design. And we have reduced clock tree power by almost 40 percent in one multimedia chip using optimized clock constraints generated from ClockExplorer."
Dr. Zachary Yao, CAD director from Monolithic Power Systems said, "Over the last two years, we have successfully used multiple analog and mixed-signal tools from ICScape. Aeolus' parallel simulation (multi-threading) capability has significantly improved our design productivity without losing accuracy. After tens of successful tapeouts, the tools are used on every design prior to tapeout."
Dr. Michael Jin, VP of R&D at iWatt, a power-management IC company said, "Interconnect extraction and analysis has always been a bottleneck in our design flow, and is becoming a critical obstacle now, especially for our power management designs. We knew we needed a tool that plugs into Virtuoso to do interactive interconnect extraction and analysis such as pin-to-pin resistance check, point-to-point resistance check, pin-to-pin delay analysis and interconnect bottleneck analysis. After a rigorous evaluation using our real, production designs, we determined that ICScape's RCExplorer demonstrated an extremely high level of performance and accuracy. Plus, the tool was easy to integrate into our existing design environment."
ICScape will be demonstrating TimingExplorer, ClockExplorer and the full A/MS flow at the Design Automation Conference (DAC) in San Francisco, June 2012 in Booth #1602.
Go to the ICScape, Inc. website to find additional information.