May 15, 2012 -- Altis Semiconductor today announced the release of its fully qualified process design kits (PDKs) for its 13-nm specialty technologies: the baseline mixed-mode CMOS (ATS-130-LP), RF-CMOS (ATS-130-RF) and embedded-Flash (ATS-130-FL).

Based on industry-proven Cadence Design Systems, Inc. Virtuoso v6.1 and OpenAccess Platform solutions, the new PDKs significantly extend the capabilities of previous versions, with enhanced functionalities and expanded EDA tool support providing customers with faster time to tape-out.

The PDKs provide easier maintenance of the different process variants such as low-power, RF, or embedded-Flash, as well as for the different metal-stack options using the ITDB (Incremental Tech Data Base) and single-source concept. Available for 0.13-µm ATS130LP/ RF/ FL, the Altis PDK suite lets designers rapidly move from concept to silicon with an enhanced "look & feel" user interface targeted for cost-effective analog/ mixed-signal design tools and RF-specialty designs. Altis provides the migration scripts to ease the transfer of existing legacy designs to the new PDK structure.

The PDK contains a set of SKILL parameterized cell generators and supports advanced interactive and automation technologies such as design-rule-driven editing and the Virtuoso Space-based Router for custom chip, block and device-level routing. Interoperability between the analog and digital flow is enabled to support the mixed-signal design flow. The Virtuoso analog technology file is incrementally augmented with place-and-route information for Cadence Encounter Digital Implementation.

To enable first-time silicon success, Altis deploys Cadence QRC Extraction and Mentor Graphics Calibre xRC for parasitic extraction.

Full support of Agilent Momentum is offered to enable 3D planar electromagnetic simulations of RF passive components, analysis of high-frequency effects related to on-chip interconnects and other critical layout structures. Agilent's GoldenGate RFIC simulator has been fully qualified with Altis models and enables full characterization of complete transceivers prior to tape-out. Both tools are seamlessly integrated into the Cadence Virtuoso Platform.

The ATS130 PDK suite comes with silicon-qualified digital, analog and RF library elements, complete sets of low voltage devices (1.2V, 1.5V, 3.3V) with an available ATS130FL 5.0-V device, and various analog devices that support low-noise and low-power applications. The Altis PDK's address the demands of complex RFIC and automotive designs with automotive-qualified digital standard cell libraries (gate density up to 203kGates/mm²) and performance enhanced 3.3-V and 5-V I/O pad libraries.