May 15, 2012 -- Cadence Design Systems, Inc. continued its efforts to help reduce time-to-market for new systems and SOCs with the announcement of new in-circuit acceleration based on the Incisive and Palladium XP platforms for its System Development Suite, and extensions to its verification IP catalog for acceleration and emulation to give engineers the ability to go beyond simulation to speed verification of large-scale SOCs, sub-systems and systems.

In-circuit acceleration added to System Development Suite (SDS)

The effort and cost associated with utilizing different, disconnected engines for virtual prototyping, RTL simulation, acceleration, emulation, and FPGA-based prototyping pose key challenges to delivering products on time. Expanding upon its in-circuit emulation technology and integrated simulation-acceleration and emulation environment, Cadence now offers as part of the System Development Suite a single heterogeneous environment for system-level verification based on the Incisive and Palladium XP platforms. This enables designers to leverage both the high-speed and real-world interfaces of traditional in-circuit emulation environments combined with the advanced analysis capabilities available in RTL simulation. Design teams are no longer forced to create and maintain both environments.

New in-circuit acceleration enables teams for simulation acceleration and emulation to deploy a common unified verification environment, resulting in up-to-10X increased efficiency during system-level validation and root-cause analysis. It further shortens system and SOC development times by delivering an optimal blend of performance and accuracy and optimal leverage of existing IP assets.

"Using in-circuit acceleration, we've enabled a new paradigm of system-level debug productivity while maintaining full in-circuit emulation performance," said Alex Starr, emulation architect at AMD. "We have reduced the time to closure on difficult, long-running workloads, which enables us to increase our hardware and software coverage while reducing the overall test plan execution time."

Verification IP (VIP) catalog expanded for acceleration and emulation

Universal Verification Model (UVM)-compatible Accelerated VIP lets users smoothly transition from simulation to acceleration, in-circuit acceleration, and in-circuit emulation, giving them the ability to verify complex systems and SOCs that are simply too large for effective verification using traditional RTL simulation.

The Cadence VIP catalog now includes Accelerated VIP for the following interface standards: ARM's AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4.