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OCP-IP Releases OCP 3.1 Specification into Member Review  
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May 23, 2012 -- OCP International Partnership (OCP-IP) has released the OCP 3.1 specification into member review. OCP 3.1 adds several important capabilities, including: flexible memory barriers, transaction-counting parameters, transitions from proprietary OCP RTL.Conf files to the Accellera IP-XACT metadata format, and new cache-coherence-compliance material. These new features allow engineers to leverage OCP to ensure IP reuse on the most advanced designs regardless of on-chip architecture or which processor cores are featured.

In high-performance systems featuring multiple processors, deep pipelining of memory transactions is needed to cover the high latency of external DRAM that exposes the system to complex ordering challenges where one core may see memory as inconsistent with respect to the operations of another core. By introducing memory barriers, OCP interfaces take advantage of performance-enhancing features such as write posting while using barrier commands to enforce system ordering so that other cores will see the effects of critical memory updates in the expected order.

OCP supports deep transaction pipelining across several request and response phases. As such it is valuable to understand the number of outstanding transactions that each side of the interface can manage. The new transaction-counting parameter extension in OCP 3.1 facilitates automated transaction buffer sizing, protocol checking and formal verification of OCP interfaces based on the maximum transaction count supported for each OCP tag, thread and interface.

The latest version of the specification now utilizes the industry-standard IP-XACT format as the preferred metadata format, based on a set of approved extensions proposed by the OCP-IP Metadata Working Group and deprecates the original OCP-proprietary formats. This enables ready integration of OCP-based cores into IP-XACT-compliant design environments.

Lastly, for convenience, OCP 3.1 has been re-structured separating the base Specification from the new Compliance chapters. In addition, the OCP-IP Functional Verification Working Group provided protocol compliance, configuration compliance and functional coverage point details for the cache coherence extensions that were originally introduced in OCP 3.0. This substantial addition greatly streamlines the process of verifying cache-coherent systems, which is one of the most challenging areas of functional verification.



Go to the OCP International Partnership (OCP-IP) website to find additional information.

E-mail OCP International Partnership (OCP-IP) for more information.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, OCP International Partnership (OCP-IP)
601/38510 5/23/2012 452 50


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