May 23, 2012 -- Imperas, Ltd. today announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP fast processor models have been integrated with NEC CyberWorkBench (CWB) SystemC cycle-accurate hardware models. OVP's position as the source of instruction-accurate processor core models provides additional value to CyberWorkBench's complete C/SystemC SOC design flow including ANSI-C/ SystemC synthesis, hardware/ software co-verification and C-based formal verification.

CyberWorkBench is a C-based circuit-design platform developed by NEC over the course of twenty years. CyberWorkBench is developed around the "All-in-C" paradigm that allows high-level synthesis and verification of any ANSI-C or SystemC program generating high-quality circuits. CyberWorkBench also includes software co-simulation environments and source code debuggers.

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare-metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/ TLM-2.0-based virtual platforms using the native TLM-2.0 interface available with all OVP processor models. The OVP simulator also has integration into an Eclipse IDE, enabling easy use for software developers.In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore-software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

NEC will have demos showing the integrations available for users to watch at the upcoming Design Automation Conference (DAC) in San Francisco (Booth #614).