SOCcentral: Integrating High-Level Synthesis Design into FPGA SOCs with Less Effort and Risk (DSP-FPGA 38529)

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Sunday, May 19, 2013

Integrating High-Level Synthesis Design into FPGA SOCs with Less Effort and Risk

Publication: DSP-FPGA
Contributor: Synopsys, Inc.

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May 15, 2012 -- SOCs have been the rage in ASIC markets for years, but are now becoming common in FPGAs with a soft core or external processor as the CPU. FPGA vendors estimate that approximately 50%t of FPGA designs are integrated with a CPU in some way, and they are starting to offer CPU cores integrated with FPGA fabric on a single chip. The industry now uses the term "FPGA SOCs" for these types of devices, and considering the substantial benefits to end users, this will undoubtedly continue as a long-term industry trend.

High-level synthesis (HLS) tools, if implemented correctly, can reduce the effort and risk associated with integrating custom hardware accelerators into FPGA SOCs. HLS tools present challenges for designers in system integration, verification, and validation, but there are methods that can ease these challenges so designers can reap their benefits.

By Chris Eddington. (Eddington is Senior Technical Marketing Manager for HLS at Synopsys, Inc.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the DSP-FPGA website.

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Synopsys, Inc.
on SOCcentral.com

Keywords: FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, high-level synthesis. HLS, system-on-chip, SoC, Synopsys, DSP-FPGA,

602/38529 5/15/2012 752 90

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