May 21, 2012 -- Many years ago, when the designers of digital circuits first started verifying their creations in simulators, directed tests were the norm. These tests were at the heart of a simple verification methodology; predict all of the test patterns required to exercise the design fully, encode them into a testbench and run them in a simulator. That methodology no longer works because most digital circuits have reached the size of complete systems. Nobody can predict and correctly encode all imaginable test patterns in the time available for most projects these days, so we need verification libraries that provide pre-defined, well-tested methodologies that speed up testbench creation and guarantee reliable test results.

Hardware verification languages introduced a methodology called constrained random stimulus generation, also known as constrained random testing (CRT) or constrained random verification (CRV). Another popular methodology is functional coverage (FC).

Until recently, both CRV and FC required either careful manual encoding, or the use of a specialised verification language. SystemVerilog was the first general-purpose language to provide reasonable facilities for CRV and FC, and so it has become accepted (in many designers' opinions) that you have to use SystemVerilog to perform these advanced verification methodologies.

But in late 2011, Aldec and Synthworks announced the as a contribution to the VHDL community. OS-VVM includes both CRV and FC methodologies for engineers designing ASICs and FPGA-based applications using VHDL.

By Jerry Kaczynski. (Kaczynski is a research engineer at Aldec, Inc.)