May 29, 2012 -- Flexras Technologies SAS today announced the Wasga compiler, a software tool that boosts multi-FPGA design performance. The Wasga compiler is a timing-driven, multi-FPGA partitioning tool for ASIC and SOC prototyping. It typically delivers a 10X clock frequency increase, runs fast, handles multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board, whether it's off-the-shelf or custom.

The Wasga compiler automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity, and the clock frequency constraints required for running software applications in near real-time. It maximizes prototyping system performance and solves hardware/ software-validation bottlenecks of next-generation SOCs to help meet the time-to-market challenges.

"Multi-FPGA platforms are heavily used for ASIC and SOC rapid prototyping. Existing tools notoriously fail the complex partitioning challenge. Verification engineers still rely on a cumbersome manual partitioning methodology," remarked Hayder Mrabet, Flexras' CEO. "Wasga compiler complements FPGA-based SOC prototyping with high-performance automatic partitioning. Engineers benefit from high clock frequencies, fast execution time, and unlimited design capacity."

Flexras will demonstrate the Wasga compiler at DAC Booth #2810, June 4-6, 2012, Moscone Center, San Francisco, Calif.

Availability

The Wasga compiler is available now.