June 4, 2012 -- Cadence Design Systems, Inc. today announced its collaboration with TSMC on 3D-IC design infrastructure development. TSMC and Cadence teams worked together to create and integrate features to support this new type of design, culminating in the test-chip tape-out of TSMC's first heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) vehicle. CoWoS is an integrated process technology that bonds multiple chips in a single device to reduce power, improve system performance and reduce form factor.

Cadence 3D-IC technology enables multi-chip co-design between digital, custom and package environments incorporating through-silicon vias (TSVs) on both chips and silicon carriers, and supports micro-bump alignment, placement, routing and design-for-test. It includes key 3D-IC design IP, such as a Wide IO controller and PHY to support Wide IO memories. Test modules were created using the Cadence Encounter RTL-to-GDSII flow, Virtuoso custom/ analog flow, and Allegro system-in-package solutions.

"Big leaps in electronic design don't happen without strong collaboration, and our partnership with Cadence in CoWoS design is a good example," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "For 3D-IC design ecosystem readiness, Cadence played an important role in the development of design technology and the necessary IP."