SOCcentral: Synopsys and Samsung Deliver a Complete Solution for 20-nm Node (Synopsys, Inc. 38634)

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Thursday, June 20, 2013

Synopsys and Samsung Deliver a Complete Solution for 20-nm Node

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June 4, 2012 -- Synopsys, Inc. today announced the availability of a complete solution to enable engineers to develop state-of-the-art system-on-chip (SOC) designs at Samsung's advanced 20-nm process geometry. The delivery of the solution is built on many years of close collaboration between Samsung Electronics and Synopsys R&D teams, including the tape-out of the first 20-nm chip based on Samsung's High-k metal gate process technology. The double-patterning enabled solution includes Synopsys IC Compiler place-and-route solution, physical-verification product, StarRC extraction tool, and PrimeTime timing-sign-off tool and all the required technology files, run sets, and run decks..

Samsung's qualification of Synopsys' Galaxy Implementation Platform is based on the two companies' R&D collaboration which developed comprehensive support for double-patterning technology and the hundreds of new rules related to finer geometries starting at 20nm. The Synopsys tools in the qualified flow include:

IC Compiler - Double-patterning-aware placement, extraction and routing can deliver an optimal, DPT-compliant layout while minimizing any impact on area and performance.
IC Validator - In-Design technology for fast detection and automatic repair of sign-off-level DPT decomposition violations and yield detractor patterns, accelerating design closure for manufacturing compliance.
PrimeTime - Added support for new multi-valued SPEF with minimal impact on run-time maintains sign-off timing results at 20nm, including effects of double-patterning.
StarRC - Silicon-calibrated modeling of parasitic variation addresses the effects of double-patterning technology due to mask misalignment to enable accurate and high performance design.

Go to the Synopsys, Inc. website to find additional information.

E-mail Synopsys, Inc. for more information.

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Synopsys, Inc.
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Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, Synopsys, IC Compiler place and route, place-and-route, placement and routing, StarRC parasitic extraction, parasitics, PrimeTime timing analysis, timing optimization, timing closure, IC Validator physical verification, Samsung,

601/38634 6/4/2012 475 69

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