June 4, 2012 -- Synopsys, Inc. today announced an integrated hybrid prototyping solution that combines Synopsys' Virtualizer virtual prototyping and Synopsys' HAPS FPGA-based prototyping to accelerate the development of system-on-chip (SOC) hardware and software.
By using Virtualizer virtual prototyping for new design functions and HAPS FPGA-based prototyping for reused logic, designers can start software development up to 12 months earlier in the design cycle. In addition, Synopsys' hybrid prototyping solution enables designers to accelerate hardware/ software integration and system validation, significantly reducing the overall product design cycle. With high-performance models for ARM Cortex processors, ARM AMBA protocol-based transactors, and DesignWare IP, developers can easily partition their ARM processor-based designs into virtual and FPGA-based prototypes as best suited to their design requirements.
Today, designers use two relatively independent methods for SOC prototyping: transaction-level model (TLM)-based virtual prototyping and FPGA-based prototyping. Virtual prototyping is ideal for accelerating pre-RTL software development by executing fast TLMs and provides more efficient debug and analysis scenarios. FPGA-based prototyping provides cycle-accurate, high-performance execution and direct real-world interface connectivity. Synopsys' hybrid prototyping solution blends the strengths of both Virtualizer virtual and HAPS FPGA-based prototyping to enable software development and system integration much sooner in the project lifecycle.
Synopsys' hybrid prototyping solution enhances software stack validation through very high-speed execution of processors using a Virtualizer virtual prototype. It allows direct connection to real-world I/O model interfaces through analog PHYs or test equipment attached to a HAPS FPGA-based prototype. In addition, designers can take advantage of existing RTL or IP in the FPGA-based prototype and new functions in SystemC transaction-level models, which are faster to implement and available much sooner in a project lifecycle.
Synopsys' high-performance HAPS Universal Multi-Resource Bus (UMRBus) physical link efficiently transfers data between the virtual and FPGA-based prototyping environments. The pre-verified HAPS-based transactors, supporting ARM AMBA 2.0 AHB/APB, AXI3, AXI-4 and AXI4-Lite interconnects, give designers the flexibility to partition the SOC design between the virtual or FPGA-based prototyping environments at the natural block-level boundaries of the AMBA interconnect. By using the software debug capability within the Virtualizer-based environment in a hybrid prototype, users have greater visibility and control into the register and memory files of the software under development compared to traditional FPGA-based prototyping.
The hybrid prototyping solution is available now to early adopters.
Go to the Synopsys, Inc. website to find additional information.