June 14, 2012 -- This article is based on a report that covers trends in the area of low-power design, based on an independent, global RTL power analysis and optimization survey. By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65nm and beyond.

The survey was executed in late 2011 and had 744 SOC, IC, and FPGA design professionals respond. The report analyzes the survey results and identifies relevant year-to-year trends.

The topics covered in the complete report include

Survey methodology and demographics

A blind, anonymous survey was emailed to several thousand participants worldwide by an independent consultancy during November and December 2011. 744 SOC, IC and FPGA design professionals completed the survey online. Survey respondents included a broad spectrum of designers and engineering management, with 23% of respondents in management roles — either engineering management (18%) or CAD management (5%). 14% were hardware synthesis engineers, 13% were system designers, and the remaining half covered a broad spectrum of disciplines.

Figure 1. Survey respondents' primary target technology.

Top methods used to reduce power

Clock gating was by far the most popular technique to reduce power at the RTL level, with 68 percent of respondents citing it. Power gating was number two at 35%. The second tier methods used were dynamic voltage and frequency (29%), multi Vth (24%) and resource sharing (23%).

Figure 2. Top two methods to reduce power.

The average time spent trying to meet power specifications was 26% (for those that knew how much time they spent). 61% of respondents said they spend at least 20% of their time on power-management tasks.

Top criteria for selecting RTL power optimization tools

The top criteria for selecting an RTL power optimization tool were a tie between "maximizing power reduction with minimum timing and area impact" (47%), and "accuracy of RTL power analysis" (46%). This makes sense, as the two elements work in combination: to maximize power savings at the RTL level, the RTL power estimates must be sufficiently accurate to enable designers to identify the most-efficient candidates for low-power optimizations.

The next tier factors were the "ability to easily verify that the RTL functionality is unchanged" (33%), which could be expected given that verification is a primary time sink in the design cycle, and "automatic clock gating insertion" (30%).

Figure 3. Top criteria for selecting RTL power-optimization tools.

Process nodes where RTL power optimization becomes important

Shrinking technology nodes have provided density (area) scaling; however, supply voltage scaling has almost reached a plateau by 65nm, substantially reducing the ability to achieve lower dynamic power by virtue of just scaling down technology nodes. This can explain why over half of respondents said that RTL power optimization tools became critical at 65nm and below, while over three-quarters (78%) stated they were critical at 45nm and below.

In summary

Engineers spend an average of one-quarter of their time (26%) trying to meet power specifications. For a 50 person engineering team with a cost of $10 million per year, the 26% additional overhead on designers' time associated with power-management issues equates to $2.6M annually. Over 40% of respondents stated their organizations were planning to evaluate or implement RTL power optimization tools in 2012. This high proportion indicates a growing trend to initiate more power optimization focus at the RTL rather than waiting until the later stages of design where far less impact on power can be made.. The top factors that the design community cites for selecting an RTL power-optimization tool are maximizing power reduction with minimum timing and area impact, and the accuracy of RTL power analysis. The top methods used to reduce power are clock gating and power gating.

A majority of respondents said that RTL power optimization tools became critical at 65nm and below. This is likely due to the diminishing supply-voltage scaling at smaller nodes and the demand for higher performance/ clock rates and stringent power and thermal budgets. This combination of factors is forcing designers to introduce aggressive power-reduction and power-management techniques during RTL design as they go to lower process geometries.

Shawn McCloud

Shawn McCloud is the Vice President of Marketing for Calypto Design Systems, Inc.. Prior to Calypto, Shawn was the Product Line Director for the Mentor Graphics high-level synthesis technology. Shawn also held positions at Exemplar Logic as Product Marketing Manager for RTL synthesis and Motorola as Senior System Architect for RISC- and CISC- based microprocessors. Shawn joined Calypto's executive staff in September 2011 to help shape Calypto's product lines in RTL power optimization and ESL hardware design.

To download the complete report, go to www.calypto.com/lpreport.php