May 25, 2012 -- In today's ever-shrinking VLSI world, where the technology is changing very fast and innovative and more complex architectures are being introduced every day, time-to-market still remains the key challenge for VLSI designers. In pursuit of project-cycle-time reduction various approaches are followed today.

One such approach is the parallel development of the IP along with the SOC. So late-stage integration of such critical blocks is not a rarity these days. Usually, there's an initial IP design available to the SOC team while the final delivery of the block is supposed to happen towards the end of the project. The initial design is frozen from IP-to-SOC interface perspective and interface pins are thus mutually agreed upon and are final before initiating the SOC implementation.

The conventional approach to handle such blocks is to separately harden the block so that rest of the SOC integration happens as usual and is left unaffected when the final block appears late-stage. But this approach has certain disadvantages:

To circumvent these limitations we have come up with the flow that partitions soft IP in such a manner that the overall die size is saved, timing-closure cycle is reduced, and engineering effort is reduced.

By Kushagra Khorwal, Vijay Bhargava and Abhishek Mahajan. (The authors are with Freescale Semiconductors, Inc.)